ADC ACE-COM L1 Especificaciones

Data Sheet: JN5148-001 IEEE802.15.4 Wireless Microcontroller © NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 1 Overview Features: Trans

10 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 2.1 Pin Assignment Pin No Power supplies Signal Type Description 10, 12, 16, 18, 27, 35,

100 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 Contact Details NXP Laboratories UK Ltd (Formerly Jennic Ltd) Furnival Street S

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 11 Pin No Digital Peripheral I/O Signal Type Description Primary Alternate Functions 51 D

12 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 2.2 Pin Descriptions 2.2.1 Power Supplies The device is powered from the VDD1 and VDD2 pi

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 13 2.2.5 Analogue Peripherals Several of the analogue peripherals require a reference voltag

14 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 IOIEVDD2VSSPuRPURPROTOEDIO[x] Pin Figure 4: DIO Pin Equivalent Schematic In reset, the di

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 15 3 CPU The CPU of the JN5148 is a 32-bit load and store RISC processor. It has been archi

16 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 4 Memory Organisation This section describes the different memories found within the JN51

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 17 4.2 RAM The JN5148 contains 128kBytes of high speed RAM. It can be used for both code a

18 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 At reset, the contents of this memory are copied into RAM by the software boot loader. T

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 19 5 System Clocks Two system clocks are used to provide timing references into the on-chip

2 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 Contents 1 Introduction 6 1.1 Wireless Transceiver 6 1.2 RISC CPU and Memory 6 1.3 Peri

20 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 5.2 32kHz System Clock The 32kHz system clock is used for timing the length of a sleep p

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 21 6 Reset A system reset initialises the device to a pre-defined state and forces the CPU t

22 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 RESETN C1 R1 JN5148 VDD 18k 470nF Figure 12: External Reset Generation The external res

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 23 6.4 Brown-out Detect An internal brown-out detect module is used to monitor the supply vo

24 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 7 Interrupt System The interrupt system on the JN5148 is a hardware-vectored interrupt sy

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 25 7.3 Hardware Interrupts Hardware interrupts generated from the transceiver, analogue or d

26 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 8 Wireless Transceiver The wireless transceiver comprises a 2.45GHz radio, modem, a baseb

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 27 8.1.1 Radio External Components In order to realise the full performance of the radio it

28 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 Antenna AAntenna BABCOMSELSELBADO (DIO[12])ADE (DIO[13])Device RF PortRF Switch: Single-

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 29 8.2 Modem The modem performs all the necessary modulation and spreading functions require

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 3 8 Wireless Transceiver 26 8.1 Radio 26 8.1.1 Radio External Components 27 8.1.2 Ant

30 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 8.3 Baseband Processor The baseband processor provides all time-critical functions of the

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 31 provided to indicate successful packet reception. During reception, the modem determines

32 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 8.6 Higher Data Rates To support the demands of applications that require high data throu

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 33 9 Digital Input/Output There are 21 Digital I/O (DIO) pins, which can be configured as ei

34 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 4-wireDigital AudioInterfaceAntennaDiversityJTAGDebugPulseCountersIntelligentPeripheralMU

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 35 10 Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed s

36 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 SI SO C SS Slave 0 Flash/ EEPROM Me mory JN5148 37 38 41 42 43 36 33 34 SI SO C SS Slave

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 37 sent from a slave, it should perform transmit using dummy data. An interrupt can be gene

38 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 11 Timers 11.1 Peripheral Timer/Counters Three general-purpose timer/counter units are av

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 39 The clock source for the timer unit is fed from the 16MHz system clock. This clock passes

4 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 20 Analogue Peripherals 58 20.1 Analogue to Digital Converter 59 20.1.1 Operation 59

40 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 CLKCAPTx93x 14tRISEtRISEtFALLtFALLRiseFall95 437Capture Mode Enabled Figure 28: Capture M

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 41 1 2 3 1 2 NConversion cycle 1217NConversion cycle 23 Figure 29: Return To Zero Mode in O

42 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 • 28-bit match value • Maskable timer interrupt • Single-shot, Restartable or Continuo

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 43 A wakeup timer consists of a 35-bit down counter clocked from the selected 32 kHz clock.

44 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 12 Pulse Counters Two 16-bit counters are provided that can increment during all modes of

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 45 13 Serial Communications The JN5148 has two independent Universal Asynchronous Receiver/

46 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 where the hardware controls the value of the generated RTS (negated if the receive FIFO f

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 47 14 JTAG Debug Interface The JN5148 includes an IEEE1149.1 compliant JTAG port for the sol

48 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 15 Two-Wire Serial Interface The JN5148 includes industry standard two-wire synchronous S

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 49 15.2 Clock Stretching Slave devices can use clock stretching to slow down the transfer bi

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 5 Appendix A Mechanical and Ordering Information 81 A.1 56-pin QFN Package Drawing 81 A.2

50 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 15.4 Slave Two-wire Serial Interface When operating as a slave device, the interface does

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 51 16 Four-Wire Digital Audio Interface The JN5148 includes a four-wire digital audio interf

52 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 Right R2 R1 R0 L2 L1 L0LeftData BufferSCKWSSD Max SizeSD 3-bitsMSB LSB MSB LSBLeft RightL

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 53 17 Random Number Generator A random number generator is provided which creates a 16-bit r

54 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 18 Sample FIFO A 10 deep FIFO is provided to buffer data between the CPU and either the f

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 55 19 Intelligent Peripheral Interface The Intelligent Peripheral (IP) Interface is provided

56 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 If data is queued for transmission and the recipient has indicated that they are ready fo

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 57 all the data specified in the length field to the JN5148. The master must then deassert

58 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 20 Analogue Peripherals The JN5148 contains a number of analogue peripherals allowing the

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 59 20.1 Analogue to Digital Converter The 12-bit analogue to digital converter (ADC) uses a

6 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 1 Introduction The JN5148-001 is an IEEE802.15.4 wireless microcontroller that provides a

60 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 interrupt can be modified to occur at the end of the chosen accumulation period, alternat

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 61 20.3 Comparators The JN5148 contains two analogue comparators COMP1 and COMP2 that are de

62 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 21 Power Management and Sleep Modes 21.1 Operating Modes Three operating modes are provid

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 63 and this therefore preserves any interface to the outside world. The DAC outputs are pla

64 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 22 Electrical Characteristics 22.1 Maximum Ratings Exceeding these conditions may result

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 65 22.2.2 DC Current Consumption VDD = 2.0 to 3.6V, -40 to +85º C 22.2.2.1 Active Processing

66 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 22.2.3 I/O Characteristics VDD = 2.0 to 3.6V, -40 to +85º C Parameter Min Typ Max Uni

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 67 Internal RESETRESETNVRSTtSTABtRST Figure 46: Externally Applied Reset VDD = 2.0 to 3.6V,

68 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 22.3.2 SPI MasterTiming tSSHtSSStCKtSItHIMOSI(mode=1,3)SSMOSI(mode=0,2)MISO(mode=0,2)MISO

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 69 Parameter Symbol Min Max Unit Clock period tck 125.0 - ns Data setup time tsi 15 - ns

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 7 1.3 Peripherals The following peripherals are available on chip: • Master SPI port with f

70 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 22.3.5 Four-Wire Digital Audio Interface SCKWS/SDOUTSDINtcktdtrtsrthrthctlc Parameter Sy

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 71 22.3.7 Bandgap Reference VDD = 2.0 to 3.6V, -40 to +85ºC Parameter Min Typ Max Unit

72 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 22.3.9 Digital to Analogue Converters VDD = 3.0V, VREF = 1.2V, -40 to +85ºC Parameter Mi

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 73 22.3.10 Comparators VDD = 2.0 to 3.6V -40 to +85ºC Parameter Min Typ Max Unit Notes

74 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 22.3.12 32kHz Crystal Oscillator VDD = 2.0 to 3.6V, -40 to +85ºC Parameter Min Typ M

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 75 22.3.14 24MHz RC Oscillator VDD = 2.0 to 3.6V, -40 to +85ºC Parameter Min Typ Max Un

76 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 22.3.16 Radio Transceiver This JN5148 meets all the requirements of the IEEE802.15.4 sta

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 77 Radio Parameters: 2.0-3.6V, +25ºC Parameter Min Typical Max Unit Notes Receiver Characte

78 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 Radio Parameters: 2.0-3.6V, -40ºC Parameter Min Typical Max Unit Notes Receiver Characte

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 79 Radio Parameters: 2.0-3.6V, +85ºC Parameter Min Typical Max Unit Notes Receiver Characte

8 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 1.4 Block Diagram 32-bit RISC CPU Reset SPI Master MUX UART0 UART1 Wakeup Timer1 Wakeup T

80 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 Note1: Blocker rejection is defined as the value, when 1% PER is seen with the wanted si

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 81 Appendix A Mechanical and Ordering Information A.1 56-pin QFN Package Drawing Figure 5

82 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 A.2 PCB Decal The following PCB decal is recommended; all dimensions are in millimetres

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 83 A.3 Ordering Information The standard qualification for the JN5148 is Industrial tempera

84 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 A.4 Device Package Marking The diagram below shows the package markings for JN5148. The

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 85 A.5 Tape and Reel Information A.5.1 Tape Orientation and Dimensions The general orientat

86 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 A.5.2 Reel Information: 180mm Reel Surface Resistivity Between 10e9 – 10e11 Ohms Square

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 87 A.5.3 Reel Information: 330mm Reel Surface Resistivity Between 10e9 – 10e11 Ohms Square

88 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 Appendix B Development Support B.1 Crystal Oscillators This section covers some of the ge

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 89 B.1.3 Crystal ESR and Required Transconductance The resistor in the crystal equivalent

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 9 2 Pin Configurations DIO16/RXD 1/IP_DI/JTAG_TDI DIO17/CTS 1/I P_SEL/DA I_SC K/JTAG _TCK VS

90 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 B.2 32MHz Oscillator The JN5148 contains the necessary on-chip components to build a 32

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 91 As is stated above, not all combinations of crystal load capacitance and ESR are valid,

92 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 B.3 32kHz Oscillator In order to obtain more accurate sleep periods, the JN5148 conta

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 93 Three examples of typical crystals are given, each with the value of external capacitors

94 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 B.4 JN5148 Module Reference Designs For customers wishing to integrate the JN5148 device

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 95 Component Designator Value/Type Function PCB Layout Constraints C13 10uF Power sourc

96 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 B.4.2 PCB Design and Reflow Profile PCB and land pattern designs are key to the reliabil

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 97 Related Documents [1] IEEE Std 802.15.4-2003 IEEE Standard for Information Technology –

98 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 Disclaimers Limited warranty and liability — Information in this document is believed to

© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 99 Version Control Version Notes 1.0 12th December 2008 – First issue, released as Advance I