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LTC4261/LTC4261-2

42612fd

For more information www.linear.com/LTC4261

Figure 6. Overcurrent Fault and Auto-Retry

In the case of a low impedance short circuit on the load

side or an input step during battery replacement, current

overshoot is inevitable. A fast SENSE comparator with a

threshold of 250mV detects the overshoot and immedi

ately pulls GATE low. Once the SENSE voltage drops to

50mV, the current limit loop takes over and ser

vos the

current as previously described. If the short-circuit con

dition lasts longer than 530µs, the FET is shut down and

the overcurrent fault is registered.

In the case of an input step, after an internal clamp pulls the

RAMP pin down to 1.1V, the inrush control circuit takes

over and the current limit loop is disengaged before the

circuit breaker timer expires. From this point on, the device

works as in the initial start-up: V

OUT

is ramped down at the

rate set by I

RAMP

and C

followed by GATE pull-up. The

power good signals on the PG and PGIO pins, the TMR

pin, and the SS pin are not interrupted through the input

step sequence. The waveform in Figure 7 shows how the

LTC4261/LTC4261-2 responds to an input step.

Note that the current limit threshold should be set

sufﬁciently high to accommodate the sum of the load

current and the inrush current to avoid engagement of

the current limit loop in the event of an input step. The

maximum value of the inrush current is given by:

INRUSH

≤ 0.8 •

45mV

– I

LOAD

where the 0.8 factor is used as a worst case margin com-

bined with the minumum threshold (45mV).

The active current limit circuit is compensated using the

capacitor C

with a series resistor R

(10W) connected

between GATE and V

, as shown in Figure 1. The sug-

gested value for C

is 50nF. This value should work for

most pass transistors (Q1).

Overvoltage Fault

An overvoltage fault occurs when the OV pin rises above

its 1.77V threshold. This shuts off the pass transistor

immediately, sets the overvoltage present bit A0 and

the overvoltage fault bit B0, and pulls the SS pin down.

Note that the power good signals are not affected by the

overvoltage fault. If the OV pin subsequently falls back

below the threshold, the pass transistor will be allowed

to turn on again immediately (without delay) unless the

APPLICATIONS INFORMATION

TMR

GATE

OUT

SENSE

PGIO

OC COOLING DELAY

PWRGD1

DELAY

– 1.2V

1.77V

INRUSH

PWRGD2

DELAY

50mV

530µs

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