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Introduction

Scope of this Application Report

This application report describes how to construct 12-bit data acquisition systems using the TLC2543 serial-out

analog-to-digital converter (ADC) in conjunction with a range of four popular microcontrollers.

The four microcontrollers used are the TMS370, H8/300, 68HC11 and 80C51.

The TLC2543

The TLC2543 is a 12-bit ADC which uses the switched capacitor successive approximation technique to perform the

conversion process and provides a maximum sampling rate of 66k samples per second (KSPS) while using only 1 mA

(typical) of supply current.

The block diagram of the TLC2543 is shown in Figure 1. Any one of eleven analog input channels can be selected by

programming the four most significant bits (MSBs) of the eight bit channel/mode control byte applied serially to the

DATA INPUT terminal of the device. In addition three internal test voltages [ V

ref–

, V

ref+

and (V

ref+

– V

ref–

)/2] can

be applied to the converter for calibration or other purposes by applying the appropriate code to the same four MSBs.

The four least significant bits (LSBs) of the channel/mode control byte are used to select the output data length (8, 12

or 16 bits), the output data order (MSB first or LSB first) and whether unipolar (binary) or bipolar (2’s complement

around (V

ref+

– V

ref–

)/2) format is required.

• 12-Bit Resolution ADC

• 66-KSPS Sampling Rate

• 11 Analog Input Channels

• Low Supply Current –1 mA (Typ)

• Power-Down Mode –4 µA (Typ)

• SPI Compatible Serial Interface

14-Channel

Analog Input

MUX

Input

Address

Control

Logic

Sample

and

Hold

12-Bit

ADC

Output

Data

Parallel

To Serial

Converter

Self-Test

Reference

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

Data

Input

I/O Clock

Serial

Data Out

EOC

Analog

Inputs

Figure 1. TLC2543 Block Diagram

Interface Timing

Four transfer methods are available for obtaining the full 12 bits of resolution from the TLC2543. Either 12 or 16 clock

cycles can be used for each conversion and data transfer.

A chip select (CS) pulse can be inserted at the start of each conversion or only once at the beginning of each sequence

of conversions with CS remaining low until the sequence is completed.

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