ADC PWR-AVIS Manual de usuario descargar pdf (Pagina 7)

LTC2245

2245fa

TYPICAL PERFOR A CE CHARACTERISTICS

OVDD

vs Sample Rate, 5MHz Sine

Wave Input, –1dB, O

VDD

= 1.8V

VDD

vs Sample Rate,

5MHz Sine Wave Input, –1dB

PI FU CTIO S

+ (Pin 1): Positive Differential Analog Input.

- (Pin 2): Negative Differential Analog Input.

REFH (Pins 3, 4): ADC High Reference. Short together and

bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as

close to the pin as possible. Also bypass to pins 5, 6 with

an additional 2.2µF ceramic chip capacitor and to ground

with a 1µF ceramic chip capacitor.

REFL (Pins 5, 6): ADC Low Reference. Short together and

bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as

close to the pin as possible. Also bypass to pins 3, 4 with

an additional 2.2µF ceramic chip capacitor and to ground

with a 1µF ceramic chip capacitor.

(Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF

ceramic chip capacitors.

GND (Pin 8): ADC Power Ground.

CLK (Pin 9): Clock Input. The input sample starts on the

positive edge.

SHDN (Pin 10): Shutdown Mode Selection Pin. Connect-

ing SHDN to GND and OE to GND results in normal

operation with the outputs enabled. Connecting SHDN to

GND and OE to V

results in normal operation with the

outputs at high impedance. Connecting SHDN to V

and

OE to GND results in nap mode with the outputs at high

impedance. Connecting SHDN to V

and OE to V

results in sleep mode with the outputs at high impedance.

OE (Pin 11): Output Enable Pin. Refer to SHDN pin

function.

D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24,

25, 26, 27): Digital Outputs. D13 is the MSB.

OGND (Pin 20): Output Driver Ground.

(Pin 21): Positive Supply for the Output Drivers.

Bypass to ground with 0.1µF ceramic chip capacitor.

OF (Pin 28): Over/Under Flow Output. High when an over

or under flow has occurred.

MODE (Pin 29): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Connecting MODE to GND selects

offset binary output format and turns the clock duty cycle

stabilizer off. 1/3 V

selects offset binary output format

and turns the clock duty cycle stabilizer on. 2/3 V

selects

2’s complement output format and turns the clock duty

cycle stabilizer on. V

selects 2’s complement output

format and turns the clock duty cycle stabilizer off.

SAMPLE RATE (Msps)

VDD

(mA)

02468

2245 G12

10 12 14

2V RANGE

1V RANGE

SAMPLE RATE (Msps)

OVDD

(mA)

0.1

0.3

0.4

0.5

1.0

0.7

2245 G13

0.2

0.8

0.9

0.6

1 2 3 4 5 6 7 8 9 10 11 12 ... 19 20

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ADC PWR-AVIS Manual de usuario Pagina 7

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