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ADS7865

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SBAS441C –OCTOBER 2008–REVISED APRIL 2012

Sequencer Register

A/B data of the second-last channel in the sequence,

and so on. Trying to read out more results (2, 4, or 6)

The ADS7865 features a programmable sequencer

than the actual sequence length results in 000h at the

that controls the switching of the ADC input

output of the converter. Older conversion results are

multiplexer. To set up the sequencer, two write

overwritten if all data of a completed sequence have

accesses to the ADC are required. During the first

not been read out before issuing a new conversion

write access, the programming of the sequencer must

start. Figure 34 shows an example where the

be enabled by setting R[1:0] = '01' and A[2:0] = '100'

sequencer is set to scan through the pseudo-

in the Configuration Register. The data applied to the

differential inputs of the ADS7865 beginning with

data bus on the second write access contain the

CHx1+, followed by CHx1– and CHx0+, while using a

updated Sequencer Register content.

single CONVST and BUSY for the entire sequence.

The structure of the Sequencer Register is shown in The internal LIFO pointer is reset with every BUSY

Table 9. The default value of this register after power- signal rising edge. Therefore, to ensure proper data

up is 0x000. retrieval, the sequence results should either be read

after completion of the entire sequence conversion or

Detailed timing diagrams of the different sequencer

between two consecutive conversions within the

modes are shown in Figure 33.

sequence as indicated in Figure 34. Other read

options may deliver incorrect results.

If the output data are read after the entire sequence

has been converted, the output data are presented in

LIFO manner (last in, first out); that is, the conversion

results of ADC A is followed by ADC B data of the

last channel in the sequence, followed by the ADC

Table 9. Sequencer Register Map

SEQUENCER REGISTER BIT

11 10 9 8 7 6 5 4 3 2 1 0

S1 S0 SL1 SL0 CH1 CM1 CH2 CM2 CH3 CM3 SP1 SP0

Table 10. S1 and S0: Sequencer Mode

S1 S0 FUNCTION

0 X Individual CONVST and BUSY for each conversion

Single CONVST for entire sequence and individual BUSY for each

1 0

conversion

1 1 Single CONVST and BUSY for entire sequence

Table 11. SL1 and SL0: Sequence Length

SL1 SL0 FUNCTION

0 0 Length = 0: Sequencer disabled

0 1 Length = 1: Cx1 (bits 6/7) enabled

1 0 Length = 2: Cx1 (bits 6/7) and Cx2 (bits 4/5) enabled

1 1 Length = 3: Cx1 (bits 6/7), Cx2 (bits 4/5), and Cx3 (bits 2/3) enabled

CH1: Signal input of the first channel in sequence; refer to Table 12 for details.

CM1: Common-mode input of the first channel in sequence; refer to Table 12 for details.

CH2: Signal input of the second channel in sequence; refer to Table 12 for details.

CM2: Common-mode input of the second channel in sequence; refer to Table 12 for details.

CH3: Signal input of the third channel in sequence; refer to Table 12 for details.

CM3: Common-mode input of the third channel in sequence; refer to Table 12 for details.

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 32 33

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